1. Field of the Invention
The present invention relates to command signal generator circuits, and more particularly to a command signal generator circuit for resetting initial conditions in a CMOS integrated circuit.
2. Discussion of the Related Art
In a broad variety of integrated circuit devices there are required operations for resetting the devices to initial conditions which are pre-set upon starting of the device. For example, the logic states in memory devices may be zeroed or reset.
If no special signal from the outside of the device is available, there must be provided a circuit designed to generate a command signal in the integrated circuit to cause initiation of the required resetting operations.
The command circuit is required to intervene not only upon starting the device but also whenever the supply voltage falls beneath a minimum level thereby jeopardizing the performance of the device.
The type of circuit for resetting a device to initial operating conditions is generally termed a "power-on reset" circuit in the technical literature. The acronym POR is derived from this circuit name and is also used.
A power-on reset circuit generates an output pulse when an input voltage signal (VDD) exceeds a first pre-set voltage. The power-on reset circuit also has hysteresis, i.e., the circuit repositions itself under initial conditions and is thus capable of generating a new pulse every time the input voltage signal (VDD) falls below a second preset voltage determined also on the basis of design parameters.
Upon starting of the device, this circuit finds an immediate application, as mentioned, as an automatic and internal generator, of a reset pulse in an integrated circuit.
A power-on reset circuit is a circuit which reads rise or fall ramps on the supply voltage and generates a pulse at a pre-set point on the ramps.
The basic characteristics of this type of circuit are the following.
The reset pulse must be generated independently of the rise and fall time of the supply voltage. These times vary typically by a few tenths of a msec to a few nsec. In addition, a circuit of this type must react correctly to a highly oscillating input waveform during settling time to the final pre-set value.
The minimum time necessary for the circuit to be able to generate a new pulse is called "recovery time".
The minimum time necessary from supply voltage fall to permit regeneration of a new pulse is called "minimum VDD break time".
Minimum current consumption is important when the device is under so-called standby conditions and this aspect is very important especially for CMOS devices. The so-called standby conditions refer to normal operating conditions of the CMOS devices while the voltage supply (VDD) is stable.
The lower voltage threshold to which the supply voltage must fall to permit the POR circuit to generate a new reset pulse for the device is called "minimum VDD bump". Indeed, there must be generated new power-on pulses when the supply voltage falls below a minimum value for which it can no longer be said that the device is holding correct initial conditions.
One of the drawbacks of this type of circuit is that it is difficult to provide a power-on reset circuit with null current draw under stand-by conditions while achieving the other characteristics such as minimum VDD break time and VDD bump.
To meet these requirements those skilled in the art have conceived and implemented numerous power-on reset circuits with different technologies linked to the different types of devices.
One possible embodiment in CMOS technology is described, e.g., in U.S. Pat. No. 4,888,497 of this applicant.
A mixed technology embodiment is indicated in European Patent Application Ser. No. 92830336.1 also by this applicant.